wip refactor
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%include "fn.s"
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%include "ps2.s"
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%macro mov_out 3
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mov %1, %3
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out %2, %1
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%endmacro
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; Check whether the A20 line is enabled. Writes to the boot sector identifier.
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; Arguments: none
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; Return:
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; - ax: 0 if A20 disabled, nonzero if A20 enabled
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; Clobber: none
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test_a20:
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push bp
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mov bp, sp
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push gs
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; Restore the boot sector identifier in case it was overwritten by anything.
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mov word [0x7dfe], 0xaa55
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mov ax, 0xffff
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mov gs, ax
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xor ax, ax
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; If the word at 0x107dfe (1 MiB after the boot sector identifier) is different to the boot
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; sector identifier, than A20 must be enabled.
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cmp word gs:[0x7e0e], 0xaa55
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setne al
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jne .return
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; Even if A20 was enabled, the two words may have been equal by chance, so we temporarily swap
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; the boot sector identifier bytes and test again.
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ror word [0x7dfe], 8
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cmp word gs:[0x7e0e], 0x55aa
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setne al
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ror word [0x7dfe], 8
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jmp .return
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.return:
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pop gs
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pop bp
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ret
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global test_a20
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; Try to enable A20 using the Intel 8042 PS/2 keyboard controller.
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; Arguments: none
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; Return: none
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; Clobber: ax, cx, dx
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enable_a20_intel_8042:
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; Temporarily disable the keyboard.
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call intel_8042_wait_write
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mov_out al, INTEL_8042_OUT_CMD, INTEL_8042_CMD_PS2_1_DISABLE
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; Read the controller output port.
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call intel_8042_wait_write
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mov_out al, INTEL_8042_OUT_CMD, INTEL_8042_CMD_CONTROLLER_OUT_PORT_READ
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call intel_8042_wait_read
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in al, INTEL_8042_IO_DATA
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; The second bit is "A20 enabled", so set it.
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mov cl, al
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or cl, 2
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; Write the modified byte back to the controller output port.
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call intel_8042_wait_write
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mov_out al, INTEL_8042_OUT_CMD, INTEL_8042_CMD_CONTROLLER_OUT_PORT_WRITE
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call intel_8042_wait_write
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mov_out al, INTEL_8042_IO_DATA, cl
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; Re-enable the keyboard.
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call intel_8042_wait_write
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mov_out al, INTEL_8042_OUT_CMD, INTEL_8042_CMD_PS2_1_ENABLE
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; Wait for writes to finish.
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call intel_8042_wait_write
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ret
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global enable_a20_intel_8042
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; Wait for the Intel 8042 input buffer to become empty, so we can write.
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; Arguments: none
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; Return: none
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; Clobber: al
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intel_8042_wait_write:
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.loop:
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; Read the 8042 status register.
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in al, INTEL_8042_IN_STATUS
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; Input buffer status flag set means the input buffer is full, so loop in this case.
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test al, INTEL_8042_STATUS_MASK_IBUF
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jnz .loop
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ret
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; Wait for the Intel 8042 output buffer to become filled, so we can read.
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; Arguments: none
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; Return: none
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; Clobber: al
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intel_8042_wait_read:
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.loop:
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; Read the 8042 status register.
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in al, INTEL_8042_IN_STATUS
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; Output buffer status flag unset means output buffer is empty, so loop in this case.
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test al, INTEL_8042_STATUS_MASK_OBUF
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jz .loop
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ret
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+180
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[bits 16]
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%include "fn.s"
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%include "layout.s"
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%include "s2_fns.s"
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extern test_a20
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extern enable_a20_intel_8042
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section .s3_text
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s3_main:
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call test_a20
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test al, al
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jnz .a20_enabled
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; Try to enable A20 using the Intel 8042 PS/2 keyboard controller.
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call enable_a20_intel_8042
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call test_a20
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test al, al
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jnz .a20_enabled
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; TODO: try other methods first before we panic:
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; - [ ] BIOS interrupt
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; - [ ] Fast A20 enable
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jmp panic_simple
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.a20_enabled:
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mov ax, 0x0003
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int 0x10
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; Disable cursor
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mov ax, 0x0100
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mov cx, 0x3f00
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int 0x10
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; Ensure interrupts are definitely disabled.
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cli
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; Load our flat-address-space GDT.
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lgdt [gdt_flat_slice]
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; Set the protected-mode bit in cr0.
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mov eax, cr0
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or al, 0x01
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mov cr0, eax
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; Long jump to set the code segment to gdt_flat.segment_code, and to clear the instruction
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; pipeline.
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jmp GDT_FLAT_IDX_CODE_32:.protected_mode_32
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[bits 32]
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.protected_mode_32:
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; Set the data segments to gdt_flat.segment_data.
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mov eax, GDT_FLAT_IDX_DATA
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mov ds, eax
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mov es, eax
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mov fs, eax
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mov gs, eax
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mov ss, eax
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; Reset the stack.
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; TODO: put the 32-bit stack somewhere else.
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mov ebp, REAL_STACK_BASE
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mov esp, ebp
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; TODO
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; jmp _start
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.halt:
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hlt
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jmp .halt
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; panic_simple_32:
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; mov word [0xb8000], 0x4f21
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; .halt:
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; hlt
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; jmp .halt
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global s3_main
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section .s3_data
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gdt_flat_slice:
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dw GDT_FLAT_LEN
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dd gdt_flat
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global gdt_flat_slice
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; Segment descriptor layout
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; | Range (bits) | Field |
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; |--------------|---------------|
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; | 0-16 | limit |
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; | 16-32 | base |
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; | 32-40 | base cont. |
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; | 40-48 | access |
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; | 48-52 | limit cont. |
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; | 52-56 | flags |
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; | 56-64 | base cont. |
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;
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; Flags
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; - 0: reserved
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; - 1: long-mode code segment
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; - 2: size
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; - unset: 16-bit
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; - set: 32-bit
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; - 3: granularity
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; - unset: limit is measured in bytes
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; - set: limit is measured in 4KiB pages
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;
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; Access
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; - 0: accessed
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; - unset: CPU will set it when the segment is accessed
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; - 1: readable / writable
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; - data segments: is segment writable (data segments are always readable)
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; - code segments: is segment readable (code segments are never writable)
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; - 2: direction / conforming
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; - data segments: whether segment grows down
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; - code segments: whether this can be executed from a lower-privilege ring
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; - 3: executable
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; - unset: this is a data segment
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; - set: this is a code segment
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; - 4: descriptor type
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; - unset: this is a task state segment
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; - set: this is a data or code segment
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; - 5-6: privilege level (ring number)
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; - 7: present (must be set)
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;
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; FIXME: copy this to a fixed memory location
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align 8
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gdt_flat:
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; First GDT entry must be 0.
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dq 0
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; 32-bit code segment.
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; Bytes 0x0000 - 0xffff.
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.segment_code_32:
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db 0xff, 0xff, \
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0x00, 0x00, \
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0x00, \
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10011011b, \
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01000000b, \
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0x00
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; 16-bit code segment, to use if we want to switch back to real mode.
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; Bytes 0x0000 - 0xffff.
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.segment_code_16:
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db 0xff, 0xff, \
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0x00, 0x00, \
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0x00, \
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10011011b, \
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00000000b, \
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0x00
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; Data segment.
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; Pages 0x000000 - 0x0fffff, which covers the entire 32-bit address space (start of 0xfffff-th page
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; is 0xfffff * 4096 = 0xfffff000, end of page exclusive is 0xfffff000 + 4096 = 0x100000000).
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.segment_data:
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db 0xff, 0xff, \
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0x00, 0x00, \
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0x00, \
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10010011b, \
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11001111b, \
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0x00
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global gdt_flat
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GDT_FLAT_LEN equ ($ - gdt_flat)
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GDT_FLAT_IDX_CODE_32 equ (gdt_flat.segment_code_32 - gdt_flat)
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global GDT_FLAT_IDX_CODE_32
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GDT_FLAT_IDX_CODE_16 equ (gdt_flat.segment_code_16 - gdt_flat)
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global GDT_FLAT_IDX_CODE_16
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GDT_FLAT_IDX_DATA equ (gdt_flat.segment_data - gdt_flat)
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global GDT_FLAT_IDX_DATA
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